D - Scene ~ Bridging from CAD to ATE over the VLSI ravine

Perhaps the most significant trend in the automated test equipment industry is the move toward fully integrating ATE into the CAD environment. ATE has traditionally been isolated from CAD; this gap is a serious one in terms of turnaround in VLSI device development and production. It is particularly serious in the context of semicustom VLSI chips, where an application-specific IC must be produced in a limited volume. A long, costly development and test cycle is not affordable, yet fairly stringent requirements remain. Automating the CAD/ ATE link is a key to this problem, but numerous difficulties must be overcome. The ideal procedure, from a test standpoint, would be to use the output of a fault simulator to automatically produce the entire test-generation program. What actually takes place falls far short of this goal. The functional waveforms output by the simulator, representing the waveforms at the I/O pins of an integrated circuit under test, are the simulator's only contribution to test generation. The other characteristics of interest-dc values, such as leakage currents and capacitance, and ac values, such as propagation delays within the chip-are present as parameters in the simulator model. While these parameters are effective as determinants of the simulator outputs, they themselves are not output by the simulator. Instead, the test engineer must develop programs incorporating these parameters, drawing on specifications in data sheets to do so. It is the combination of functional waveforms from the simulator and these additional handdeveloped programs that create the test program. Thus, the fully automated link between CAD and ATE remains elusive. The obstacles to combining the two worlds are actually more formidable than they appear. As Chet Sylvestri, director of marketing at Megatest, points out, fully automated operations do not exist on either side of the CAD/ATE boundary. "Automation is still in its infancy," says Sylvestri. "Even the design tools to make the chips aren't fully automated. Parts of the design are still done by hand." Keith Berger, MOS microprocessor test engineering manager at Advanced Micro Devices, remarks that "a design engineer doesn't buy a simulator because it's a good test vector generator. He gets one that helps him to design the circuit and to prove that it works." Berger also notes that (compared with a semicustom environment) the production of VLSI circuits for high-volume distribution entails a much more thorough verification of the timing relationships on the circuit. "That's a complex task," says Berger, "and so far I don't see any major advances in technology to solve that problem. " He believes that, even if the test program generation were fully automated (involving the incorporation of the entire device data sheet into a program) the resulting test procedure would not be optimal. The procedure also would not allow testing large numbers of the devices at a production rate. The semicustom area appears to be better terrain for full test automation. A skeleton program for a particular test system can utilize variables for such parameters as pin assignments, and these variables can be specified as gate arrays and other custom chips take specific forms. The semicustom chip thus becomes a natural vehicle for a semicustom test program. "When you talk about automatic program generation," says AMD's Berger, "it's the gate array people who are really going to do the initial work." The reasons are economic: With specific customers buying chip lots numbering only in the thousands, it isn't feasible to spend two years to develop a test program that tests everything on the data sheet.